1. Field of the Invention
The present invention relates to a method of fabricating a CMOS thin film transistor, and more particularly to a method of fabricating a CMOS thin film transistor that reduces an off current of an n-type thin film transistor.
2. Discussion of the Related Art
Generally, in a CMOS thin film transistor (TFT), the n-type TFT has a high current driving ratio when in the “ON” state, but a large leakage current in the “OFF” state. When used in a liquid crystal display (LCD), the large leakage current of the n-type TFT changes the value of a signal stored in a pixel electrode, which leads to reduced picture quality. Accordingly, to reduce leakage, n-type TFTs having LDD (lightly doped drain) structures or offset structures have been suggested.
FIG. 1A to FIG. 1D are sectional views representing a method of fabricating a conventional CMOS-TFT.
Referring to FIG. 1A, a silicon oxide is deposited on a transparent substrate 11, such as glass, using the chemical vapor deposition (CVD) technique, thereby forming a buffer layer 13. The substrate 11 includes a p-type transistor area P1 and an n-type transistor area N1. A polycrystalline silicon layer is then formed on the buffer layer 13 and patterned by photolithography to form first and second active layers 15 and 16 at the p-type transistor area P1 and the n-type transistor area N1, respectively.
Referring now to FIG. 1B, a silicon oxide is deposited on the buffer layer 13 by the CVD technique so as to cover the first and second active layers 15 and 16, thereby forming an insulating material film. Then, a conductive metal such as aluminum (Al) or copper (Cu) is deposited onto the insulating material film by sputtering to form a conductive metal film.
The conductive metal film and the insulating material film are then patterned by photolithography so as remain only on the middle portions of the first and second active layers 15 and 16. Thus, both sides of the first and second active layers 15 and 16 are exposed. The insulating material film remaining on the first and second active layers 15 and 16 becomes a gate insulating film 18. The conductive metal film remaining over the first active layer 15 becomes a first electrode 20. The conductive metal film remaining over the second active layer 16 becomes a second gate electrode 21.
Subsequently, the first and second active layers 15 and 16 are doped with n-type impurity ions, such as P or As, at a low concentration while using the first and second gate electrodes 20 and 21 as masks. The result is first and second low-concentrated impurity areas 23 and 24.
Referring to FIG. 1C, a photoresist is then coated on the transparent substrate 11. That photoresist is then patterned by exposure and development to form a first photoresist pattern 25 that covers the n-type transistor area N1. At this time, the entire surface of the first low-concentrated impurity area 23 within the p-type transistor area P1 is exposed.
The exposed portion of the first low-concentrated impurity area 23 (see FIG. 1B) is then ion-doped with a p-type impurity, such as B or BF2, at a high concentration using the first gate electrode 20 and the first photoresist pattern 25 as masks. The result is a first high-concentrated impurity area 27, which becomes source and drain areas of the p-type TFT. In this case, the first high-concentrated impurity area 27 is formed by doping a p-type impurity at a high concentration such that the first low-concentration impurity area 23 doped with an n-type impurity is counter-doped with a p-type impurity. The portion of the first active layer 15 under the first gate electrode 20 becomes a channel area of the p-type TFT.
Referring to FIG. 1D, the first photoresist pattern 25 is then removed. Then, a second photoresist layer 29 is coated on the transparent substrate 11. Thereafter, the second photoresist layer is exposed and developed to leave the second photoresist pattern 29 over the entire p-type transistor area P1, and to form a photoresist pattern 25 over a desired portion of the second active layer 16. That desired portion is adjacent the second gate electrode 21. The result is that part of the second low-concentrated impurity area 24 is exposed, and part is covered by the photoresist pattern 25.
The exposed portion of the second low-concentrated impurity area 24 is then doped with n-type impurity ions, such as P or As, at a high concentration using the photoresist pattern 25 as a mask. The result is a second high-concentrated impurity area 31, which becomes source and drain areas of the n-type TFT. The second low-concentrated impurity area 24 that remains becomes an LDD (lightly doped drain) area of the n-type TFT. The portion of the second active layer 16 under the second gate electrode 21 becomes a channel area of the n-type TFT.
Thereafter, although not shown, the second photoresist pattern 29 and the photoresist pattern 25 are removed.
While useful, the conventional CMOS-TFT fabricating method described above has a problem in that its fabrication process is rather complicated. The impurity areas of the n-type TFT and the p-type TFT require two photo processes and three ion-doping processes. Another problem is that since the LDD areas of the n-type TFT are controlled by formation of the n-type high-concentrated impurity areas, the LDD areas can have non-uniform lengths. This deteriorates the device characteristics.